#pragma once
enum SMAC_OP{
    SFMULD, //op = 00_1000_0000, execution cycle = 4
    SFMULS32, //op = 00_0100_0000, execution cycle = 4
    SFMULAD, //op = 0_1000, execution cycle = 6
    SFMULAS32, //op = 0_0100, execution cycle = 6
    SFMULBD, //op = 0_1100, execution cycle = 6
    SFMULBS32, //op = 0_0010, execution cycle = 6
    SFDOT32, //op = 00_1100_0000, execution cycle = 6
    SFCREAL32, //op = 00_0010_0000, execution cycle = 6
    SFCIMAG32, //op = 00_1010_0000, execution cycle = 6
    SFADDH16, //op = 11_0000_0000, execution cycle = 4
    SFSUBH16, //op = 11_0000_0001, execution cycle = 4
    SFMULH16, //op = 11_0000_0010, execution cycle = 4
    SFMULAH16, //op = 01110, execution cycle = 6
    SFMULBH16, //op = 01111, execution cycle = 6
    SFCMPEH16, //op = 11_0000_0011, execution cycle = 1
    SFCMPGH16, //op = 11_0000_0100, execution cycle = 1
    SFCMPLH16, //op = 11_0000_0101, execution cycle = 1
    SFHINT16, //op = 11_1000_0000, execution cycle = 3
    SFHTRU16, //op = 11_1000_0001, execution cycle = 3
    SFINTH16, //op = 11_1000_0010, execution cycle = 3
    SFINTHU16, //op = 11_1000_0011, execution cycle = 3
    SFSPHP16, //op = 11_1000_0100, execution cycle = 3
    SFHPSP16L, //op = 11_1000_0101, execution cycle = 1 OR 3 (正文与简表不同)
    SFHPSP16H, //op = 11_1000_1111, execution cycle = 1 OR 3 (正文与简表不同)
    SFMANH16, //op = 11_1000_0110, execution cycle = 1
    SFLOGH16, //op = 11_1000_0111, execution cycle = 1
    SFABSH16, //op = 11_1000_1000, execution cycle = 1
    SFMAX16, //op = 11_0000_1010, execution cycle = 1
    SFEXTS32L, //op = 11_1000_1001, execution cycle = 1
    SFEXTS32H, //op = 11_1000_1010, execution cycle = 1
    SFEXTH16LL, //op = 11_1000_1011, execution cycle = 1
    SFEXTH16LH, //op = 11_1000_1100, execution cycle = 1
    SFEXTH16HL, //op = 11_1000_1101, execution cycle = 1
    SFEXTH16HH, //op = 11_1000_1110, execution cycle = 1
    SADD32_src1_r_SMAC, //op = 01_001_11100, execution cycle = 1
    SADD32_src2_imm, //op = 01_001_01100, execution cycle = 1
    SADDU32_src1_r_SMAC, //op = 01_001_10100, execution cycle = 1
    SADDU32_src1_imm_SMAC, //op = 01_001_00100, execution cycle = 1
    SADD_src1_r_SMAC, //op = 01_001_11000, execution cycle = 1
    SADD_src2_imm, //op = 01_001_01000, execution cycle = 1
    SADDU_src1_r_SMAC, //op = 01_001_10000, execution cycle = 1
    SADDU_src1_imm_SMAC, //op = 01_001_00000, execution cycle = 1
    SADDA_src1_r_SMAC, //op = 01_001_11010, execution cycle = 2/3
    SADDA_src2_imm, //op = 01_001_01010, execution cycle = 2/3
    SSUB32_src1_r_SMAC, //op = 01_010_11100, execution cycle = 1
    SSUB32_src2_imm, //op = 01_010_01100, execution cycle = 1
    SSUBU32_src1_r_SMAC, //op = 01_010_10100, execution cycle = 1
    SSUBU32_src2_imm, //op = 01_010_00100, execution cycle = 1
    SSUB_src1_r_SMAC,  //op = 01_010_11000, execution cycle = 1
    SSUB_src2_imm, //op = 01_010_01000, execution cycle = 1
    SSUBU_src1_r_SMAC, //op = 01_010_10000, execution cycle = 1
    SSUBU_src2_imm, //op = 01_010_00000, execution cycle = 1
    SSUBA_src1_r_SMAC, //op = 01_010_11010, execution cycle = 2/3
    SSUBA_src2_imm, //op = 01_010_01010, execution cycle = 2/3
    SMULISU32_src1_r, //op = 01_011_11010, execution cycle = 3
    SMULISU32_src2_imm, //op = 01_011_01010, execution cycle = 3
    SMULIS32_src1_r, //op = 01_011_11110, execution cycle = 3
    SMULIS32_src2_imm, //op = 01_011_01110, execution cycle = 3
    SMULIU32_src1_r, //op = 01_011_10010, execution cycle = 3
    SMULIU32_src2_imm, //op = 01_011_00010, execution cycle = 3
    SMULISU_src1_r, //op = 01_011_11000, execution cycle = 3
    SMULISU_src2_imm, //op = 01_011_01000, execution cycle = 3
    SMULIS_src1_r, //op = 01_011_11100, execution cycle = 3
    SMULIS_src2_imm, //op = 01_011_01100, execution cycle = 3
    SMULIU_src1_r, //op = 01_011_10000, execution cycle = 3
    SMULIU_src2_imm, //op = 01_011_00000, execution cycle = 3
    SMULAUS32T_src1_r, //op = 11_101, execution cycle = 3
    SMULAUS32T_src2_imm, //op = 11_001, execution cycle = 3
    SMULASU32T_src1_r, //op = 11_110, execution cycle = 3
    SMULASU32T_src2_imm, //op = 11_010, execution cycle = 3
    SMULAU32T_src1_r, //op = 11_100, execution cycle = 3
    SMULAU32T_src2_imm, //op = 11_000, execution cycle = 3
    SMULAS32T_src1_r, //op = 11_111, execution cycle = 3
    SMULAS32T_src2_imm, //op = 11_011, execution cycle = 3
    SMULBUS32T_src1_r, //op = 10_101, execution cycle = 3
    SMULBUS32T_src2_imm, //op = 10_001, execution cycle = 3
    SMULBSU32T_src1_r, //op = 10_110, execution cycle = 3
    SMULBSU32T_src2_imm, //op = 10_010, execution cycle = 3
    SMULBS32T_src1_r, //op = 10_111, execution cycle = 3
    SMULBS32T_src2_imm, //op = 10_011, execution cycle = 3
    SMULBU32T_src1_r, //op = 10_100, execution cycle = 3
    SMULBU32T_src2_imm, //op = 10_000, execution cycle = 3
    SMOV_SMAC, //op = 01_110_00000, execution cycle = 1
    SMOVI_SMAC, //op 80位指令, execution cycle = 1
    SMVAGA, //op = 01_110_10000, execution cycle = 2
    SMVAAG, //op = 01_110_11000, execution cycle = 2
    SMVAAA, //op = 01_110_01000, execution cycle = 2
    SVBCAST, //op = 01_111_00000, execution cycle = 4
    SVBCAST2, //op = 01_111_10000, execution cycle = 4
    SFCMPED, //op = 10_00_000_0_00, execution cycle = 1
    SFCMPES32, //op = 10_00_000_1_00, execution cycle = 1
    SFCMPGD, //op = 10_00_001_0_00, execution cycle = 1
    SFCMPGS32, //op = 10_00_001_1_00, execution cycle = 1
    SFCMPLD, //op = 10_00_010_0_00, execution cycle = 1
    SFCMPLS32, //op = 10_00_010_1_00, execution cycle = 1
    SFDINT, //op = 10_10_000_0_00, execution cycle = 3
    SFSINT32, //op = 10_10_000_1_00, execution cycle = 3
    SFDTRU, //op = 10_10_001_0_00, execution cycle = 3
    SFSTRU32, //op = 10_10_001_1_00, execution cycle = 3
    SFINTD, //op = 10_10_010_0_00, execution cycle = 3
    SFINTDU, //op = 10_10_011_0_00, execution cycle = 3
    SFINTS32, //op = 10_10_010_1_00, execution cycle = 3
    SFINTSU32, //op = 10_10_011_1_00, execution cycle = 3
    SFDPSP32, //op = 10_10_100_0_00, execution cycle = 3
    SFSPDP32T, //op = 10_10_101_1_00, execution cycle = 1
    SFSPHDP32T, //op = 10_10_101_0_00, execution cycle = 1
    SFMAND, //op = 10_11_000_0_00, execution cycle = 1
    SFMANS32, //op = 10_11_000_1_00, execution cycle = 1
    SFLOGD, //op = 10_11_001_0_00, execution cycle = 1
    SFLOGS32, //op = 10_11_001_1_00, execution cycle = 1
    SFABSD, //op = 10_11_010_0_00, execution cycle = 1
    SFABSS32, //op = 10_11_010_1_00, execution cycle = 1
    SFRSQD, //op = 10_11_011_0_00, execution cycle = 1
    SFRSQS32, //op = 10_11_011_1_00, execution cycle = 1
    SFRCPD, //op = 10_11_100_0_00, execution cycle = 1
    SFRCPS32, //op = 10_11_100_1_00, execution cycle = 1
    SFADDD, //op = 10_01_000_0_00, execution cycle = 3
    SFADDS32, //op = 10_01_000_1_00, execution cycle = 3
    SFSUBD, //op = 10_01_001_0_00, execution cycle = 3
    SFSUBS32, //op = 10_01_001_1_00, execution cycle = 3
    SFSRT8D, //op = 0_000_1, execution cycle = 7
    SFSRT8S32, //op = 0_001_1, execution cycle = 4
    SFNORMD, //op = 0_010_1, execution cycle = 2
    SFNORMS32, //op = 0_011_1, execution cycle = 2
    //TODOszy:补全SMAC的全部操作
};